1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of forming a contact plug suitable for highly-integrated semiconductor devices.
2. Description of the Related Art
As is well known, silicon epitaxial growth (SEG) can be advantageously applied to semiconductor devices to decrease cell size, to simplify the manufacturing process and to improve the electrical properties of the device.
According to conventional methods, a silicon contact plug is formed by forming a contact hole and depositing amorphous silicon in the contact hole and then, performing planarization using a CMP process.
Thereby, a plug can be formed by using the selective epitaxial growth in order to solve problems such as gap-fill and contact resistance due to decrease of cell size. Moreover, by this conventional method it is not required to perform a CMP or silicon recess etch for plug isolation, thereby simplifying the process.
However, there are several problems to solve in applying the selective epitaxial growth (SEG).
First, there is the problem of selectivity in a pattern material (a material forming a window for SEG). That is, when a self-aligned contact (SAC) etch scheme is applied to provide a sufficient cell activation area, the surface of the nitride layer is exposed.
Furthermore, the SEG has different aspects of defects and facet generation due to the selectivity and thermal stress of the pattern material.
Generally, in LPCVD, the nitride material has difficulty in having selectivity at a temperature below 850xc2x0 C., as compared with an oxide material. Therefore, growth speed is lowered to have selectivity, thereby increasing thermal growth.
The conventional method is described in more detail with reference to the accompanying drawing figures in which FIGS. 1 to 4 are cross sectional views showing the steps of a conventional method for manufacturing semiconductor device.
Referring to FIG. 1, a gate electrode 3 is formed on a silicon substrate 1 and a sidewall spacer 5 is formed on the side of the gate electrode 3.
Then, although it is not shown in the drawings, impurity junction regions are formed by implanting impurities on the lower part of both sides of the sidewall spacer 5 on the silicon substrate 1.
An interlayer insulating layer 7 is deposited over the silicon substrate 1, including over the gate electrode 3 and the sidewall spacer 5.
Referring to FIG. 2, a plug contact hole 9 is formed to expose the impurity junction region (not shown) by performing a mask formation process using a lithography process and a patterning process on the interlayer insulating layer 7.
Referring to FIG. 3, an amorphous silicon layer 11 is deposited to fill the plug contact hole 9 on the upper part of the interlayer insulating layer 7, including the plug contact hole 9.
Referring to FIG. 4, the amorphous silicon layer 11 is etched by using chemical mechanical polishing (CMP) or a silicon recess etch process, thereby forming a contact plug 11a, which is electrically in contact with the impurity junction region (not shown) in the plug contact hole 9.
However, the conventional method has several problems, particularly in manufacturing a contact hole and a contact plug having a high aspect ratio, wherein a circuit line width is below a specified lower limit, for example, 0.16 xcexcm.
According to the conventional method, in order to form a plug with silicon, it is required to perform a CMP on the oxide layer, contact hole formation, amorphous silicon deposition and plug isolation, using a CMP or silicon reset etch. Therefore, a problem arises in that these processes result in high production costs.
Furthermore, it is difficult to prevent the generation of natural oxide layers on the interface of the cell and plug since in-situ cleaning is not performed in a tube type LPCVD. Therefore, contact resistance of polycrystalline silicon is increased by three times more than when using selective epitaxial growth (SEG).
There is an additional problem of gap-fill in silicon deposition due to the reduced contact hole size and increase of aspect ratio.
Moreover, compared with SEG, phosphorus diffusion is increased in a highly doped amorphous or polycrystalline silicon, thereby deteriorating the cell properties.
Although it is not shown in the drawings, another, alternative embodiment of the conventional method will be described in the following description.
According to the alternative embodiment, an interlayer insulating layer (not shown) is first deposited using a nitride material on a silicon substrate (not shown) having a gate electrode and an impurity junction region.
Then, a contact hole (not shown) is formed to expose the impurity junction region (not shown) by selectively patterning the interlayer insulating layer (not shown).
Subsequently, a SEG plug is formed in the contact hole (not shown) to maintain selectivity with the interlayer insulating layer (not shown) pattern of nitride material.
This embodiment has the advantages of reducing contact resistance and simplifying the formation process by selective epitaxial growth.
However, when a LPCVD method is applied to the conventional method, HCl is increased in order to maintain selectivity on the surface of nitride layer, thereby lowering the growth speed of SEG.
The nitride material has a thermal coefficient of expansion (TCE) higher than that of the silicon, thereby generating defects when using SEG due to the difference in thermal expansion.
It is also difficult to obtain process margin on the surface of the nitride layer in a UVH-CVD method.
Moreover, in the nitride layer pattern, regions having selectivity are decreased by ten times as compared to an oxide layer, at temperatures below 900xc2x0 C.
When the SEG is formed, the nitride pattern has a generation rate of defects higher than that of the oxide layer.
Furthermore, it is difficult to maintain the selectivity of the nitride layer in-situ, thereby lowering the growth speed.
As a result, thermal budget of SEG is increased and device properties deteriorate.
Moreover, overgrowth of SEG may occur according to the density and shape of the cell pattern, thereby generating problems of CMP on the interlayer insulating layer.
The present invention has been made to solve the above problems. One object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming an improved contact plug suitable for highly integrated semiconductor devices.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying the manufacturing process of the semiconductor device by using SEG in forming the plug.
Yet another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the contact resistance of the plug in forming the contact plug.
Still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing production costs by minimizing the amount of silicon source for the gap fill of the silicon plug.
And, still another object of the present invention is to provide a method of manufacturing a semiconductor device capable of minimizing the processing time of the plug by increasing the growth speed of silicon on the sidewall of the contact hole.
In order to accomplish the above objects, the present invention comprises the steps of: forming an insulating layer on a silicon substrate; forming a contact hole on the insulating layer; forming a silicon layer on the surface of the contact hole; and forming a selective conductive plug in the contact hole, having the silicon layer.
The above objects, and other features and advantages of the present invention will become more apparent after reading the following detailed description when considered in conjunction with the drawings.